1st Workshop on Flexible Network Data Plane Processing (NETPROC@ICIN2020)
During the last few years SDN and NFV technologies have been shaping the ways new telecommunication services and applications are deployed and managed. We have seen how dedicated equipment interconnected by static networks are being replaced by CoTS equipment running NFV solutions that in turn, make profit of a flexible and reconfigurable SDN-based networks.
We are observing that applications that require high performance network data management and processing are shifting from traditional Virtual Machine based solutions to new paradigms that cover a broad set of approaches, sometimes referred to as NFV acceleration solutions. All of them have in common the objective of improving the network processing performance, flexibility and cost either by trimming the number and complexity of traditional operating system software components, by bypassing traditional network stack processing or by offloading processing to reconfigurable or programmable hardware network data-planes. Moreover, an efficient network data plane processing will not only improve applications but will foster the appearance of new applications, as well as pave the way for new mechanisms supporting a seamless integration of network, compute and storage services, in what is being termed as “in-network computing”.
The complete challenge involves not only providing the low-level techniques but also but also building an overall approach to package and manage these techniques and facilitate their adoption by the industry. In this sense, proposals that could become compatible with software-network orchestration and automation techniques (such as those proposed by ETSI NFV architectural framework or IETF SFC, to name a couple of the most relevant current standardization approaches) are of particular interest.
We solicit papers that investigate novel approaches to Flexible Network Data Plane Processing. Possible topics include but are not limited to:
- Hardware Network Data Plane Processing: P4 and beyond.
- Software Data Plane programming: eBPF, XDP, DPDK, ODP, AF-XDP…
- Advanced applications of Network Data Plane Processing.
- Integration of in network processing in general NFV and SDN architectures
- Security management, development and implications of Network Data Plane Processing.
- Hybrid (network/host based) VNFs and supporting architectures.
- Performance evaluation and optimization.
- Stateful data plane processing.
- Cloudifying the Network Data Plane Processing.
- Supporting architectures.
- Improving the security of Network Data Plane Processing architectures, services and applications.
Main track: Submitted papers must be original work, not under review at other journals/conferences, and may comprise a maximum of 6 A4 (210 mm x 297 mm) pages in 2-column IEEE conference style with a minimum font size of 10 pt. Papers should be submitted electronically using the EDAS online submission system. All accepted papers must be presented by one of the authors.
Demo track: Submitted papers must be original work, not under review at other journals/conferences, and may comprise a maximum of 4 A4 (210 mm x 297 mm) pages in 2-column IEEE conference style with a minimum font size of 10 pt. Papers should be submitted electronically using the EDAS online submission system. All accepted papers must be presented by one of the authors, who must run the demonstration at the workshop.
Papers accepted for NETPROC 2019 will be included in the conference proceedings and IEEE Xplore. The IEEE reserves the right to remove any paper from IEEE Xplore if the paper is not presented at the workshop.
- Eduardo Jacob (University of the Basque Country, Spain)
- Marie-Jose Montpetit (MIT, USA)
Technical Program Committee
- Gianni Antichi (Queen Mary University of London, United Kingdom)
- Olivier Bonaventure (Université Catholique de Louvain, Belgium)
- Marc Bruyere (IIJ Innovation Institute – The University of Tokyo, Japan)
- Didier Colle (Ghent University, Belgium)
- Sonja Filiposka (SS. Cyril and Methodius University, North Macedonia)
- Vladimir Gurevich (Barefoot Networks, USA)
- Eiji Kawai (National Institute of Information and Communications Technology, Japan)
- Dirk Kutscher (University of Applied Sciences of Emden-Lee, Germany)
- Diego López (Telefonica I+D, Spain)
- Jonatas Marques (Universidade Federal do Rio Grande do Sul. Brasil)
- Jon Matías (Keynetic Technologies, Spain)
- Jörg Ott (Technical University of Munich, Germany)
- Fernando Ramos (University of Lisboa, Portugal)
- Fulvio Risso (Politecnico di Torino, Italy)
- Jose Saldaña (University of Zaragoza, Spain)
- Pontus Sköldström (Ericsson, Sweden)
- Balasz Sonkoly (Budapest University of Technology and Economics, Hungary)
- Marc Suñé (Volta Networks, Spain)
- Steve Uhlig (Queen Mary University of London, United Kingdom)
- Juanjo Unzilla (University of the Basque Country, Spain)
- Hagen Woesner (BISDN, Germany)